Conventionally, semiconductor memory devices such as dynamic random access memories (DRAMs) that have high levels of integration also have high defect rates. In particular, many defects occur in memory element regions (e.g., memory cell arrays). To repair semiconductor memory devices containing such defects, the semiconductor memory devices typically include redundant row or column structures in the memory arrays.
FIG. 1 shows a layout of a conventional semiconductor memory device, and for brevity and clarity does not illustrate any peripheral circuits. More specifically, FIG. 1 illustrates a conventional dynamic random access memory device (DRAM) 10 having a sub word line driver (SWD) structure (sometimes referred to as "a divided word line structure" or "a hierarchical structure"). U.S. Pat. No. 5,581,508, entitled "SEMICONDUCTOR MEMORY HAVING SUB-WORD LINE REPLACEMENT," and U.S. Pat. No. 5,761,135, entitled "SUB-WORD LINE DRIVERS FOR INTEGRATED CIRCUIT MEMORYDEVICES AND RELATED METHODS," which are hereby incorporated by reference, disclose known sub word line driver structures.
The DRAM device 10 includes a plurality of memory cell blocks 12 arranged in row and column directions. Each of the memory cell blocks has a plurality of sub word lines SWL extending in the row direction and a plurality of redundant sub word lines RSWL extending in the row direction. The DRAM device 10 further includes a plurality of sub word line drivers (SWD) 14, a plurality of sense amplifiers (S/A) 16, a plurality of redundant sub word line drivers (RSWD) 18, a plurality of main word line decoder drivers 22, and a plurality of redundant main word line decoder drivers 24. Although not illustrated in FIG. 1, the main word line decoder drivers 22 drive multiple main word lines, and the redundant word line decoder drivers 24 drive multiple redundant main word lines.
The DRAM device 10 further includes a plurality of sub row decoders 26 and a plurality of drivers 28. Most of the sub row decoders 26 are between one of the main word line decoder drivers 22 and one of the redundant main word line decoder drivers 24. Most of the drivers 28 are between one of the sub word line drivers 14 and one of the redundant sub word line drivers 18. As shown in FIG. 1, the memory cell blocks 12 are separated in the row direction by the sub word line drivers 14 and in the column direction by the sense amplifiers 16.
In the sub word line driver structure of FIG. 1, when a sub word line is defective, a row redundancy operation replaces a main word line and associated structures including the defective sub word line with a redundant main word line and associated redundant structures. Accordingly, the row redundancy operation deselects (or deactivates) a main word line decoder driver 22 that drives the main word line coupled to a set of sub word lines including the defective sub word line. The row redundancy operation selects (or activates) a redundant main word line decoder driver 24 that drives the redundant main word line that replaces the main word line.
FIG. 2 is a circuit diagram showing a main word line decoder driver according to a first redundancy scheme. As illustrated in FIG. 2, the main word line decoder driver 22 includes a fuse 59 for a redundancy operation. The fuse 59 is blown (or cut) during a row redundancy operation to deselect a corresponding main word line MWLi even when three decode signals DRA0, DRA1 and DRA2 are activated. This redundancy scheme has the drawback of increasing the layout area due to the fuse 59, which is in each main word line decoder driver 22.
FIG. 3 is a circuit diagram showing a main word line decoder driver according to a second redundancy scheme, and FIG. 4 is a timing diagram showing timing relationships among control signals in the main word line decoder driver of FIG. 3.
In FIGS. 3 and 4, a signal PR has a logic low level during a row precharge period (when RAS is high) and a logic high level during a row active period (when RAS is low). Decode signals DRAi (i=0, 1, 2), which are signals derived by decoding row address bit signals at a previous stage (for example, a row predecoder), designate or select a main word line MWLi. A signal PRREB controls whether a main word line or a redundant main word line is selected. The signal PRREB is at a logic low level to disable use of the main word line MWLi corresponding to the row address bit signals and selects a redundancy main word line (not shown in FIG. 3). When the signal PRREB is at a logic high level, the main word line MWLi is usable. U.S. Pat. No. 5,798,974, entitled "SEMICONDUCTOR MEMORY DEVICE REALIZING HIGH SPEED ACCESS AND LOW POWER CONSUMPTION WITH REDUNDANT CIRCUIT," which is hereby incorporated by reference, discloses the redundancy system of FIG. 3 and an address programming circuit generating the signal PRREB.
When the signal (referred to as "a row active signal") PR remains low (e.g., during a row precharge period), an output signal PDPX of a level shifter 80 remains low, and a PMOS transistor 69 and an invertor 71 precharge a main word line MWLi at a logic low level (for example, a ground voltage). When the signal PR goes to a logic high level (when a row address designating a sub word line is input), the output signal PDPX of the shifter 80 transitions from low to high, thereby turning off the PMOS transistor 69. As illustrated in FIG. 4, the decode signals DRA0-DRA2 go to a logic high level for a row address selecting the main word line MWLi. When the signal PRREB remains high, an output signal PNWR of an invertor 75 becomes high and turns on the NMOS transistor 79. This makes the invertor 71 activate the main word line MWLi. On the other hand, if the signal PRREB transitions from high to low as illustrated by the dashed line in FIG. 4, the NMOS transistor 79 remains off, and the main word line MWLi remains in a precharged state, for example, at the ground voltage.
Referring to FIG. 3, to prevent a main word line and a redundant main word line from being activated at the same time, an invertor chain 76 provides a delay in the main word line decoder driver 22. In particular, discrimination of whether row address bit signals correspond to a programmed defective row address in the address programming circuit determines whether the signal PRREB activates or deactivates a main word line corresponding to the row address bit signals. As well understood in FIG. 4, the transition of the decode signals DRA0-DRA2 precedes the transition of the signal PRREB. If invertor chain 76 of FIG. 3 were absent, a transition of the decode signals DRA0-DRA2 could activate the main word line MWLi, and then a transition of the signal PRREB during the activation of the main word line, could activate a redundancy main word line. Accordingly, without the delay chain 76, the main word line and the redundant main word line may be activated at the same time when the signal PRREB transitions from a logic high level to a logic low level as illustrated by a dashed line in FIG. 4.
According to the second redundancy scheme, a main word line decoder driver activates or deactivates a main word line MWLi after discriminating whether a row replacement is performed or not (or whether the signal PRREB is activated or not). Therefore, the invertor chain 76, which includes series-connected invertors 72 and 73, delays the activation of the signal PNWR (and activation of the main word line MWLi) by a delay time t.sub.D. This increases an access time from a row active (and reduces access speed), which is determined by t.sub.RCD +t.sub.CAC. The t.sub.RCD and t.sub.CAC indicate RAS to CAS delay and CAS latency, respectively (the t.sub.RCD is delayed by the invertor chain 76).